FIG. 1 is a cross-section of a portion of an edge of an IGTO device 32 described in Applicant's U.S. Pat. No. 8,569,117, incorporated herein by reference. The p+ guard rings 57 and 58, formed in the n− epitaxial (epi) layer 50 near the edge of the die, reduce electric field crowding near the edges of the die to improve the breakdown voltage of the IGTO device. The trenched gates may form an interconnected mesh and are electrically connected to a top metal gate electrode 44 for biasing all the gates simultaneously. The gates may be repeated as a two-dimensional array of gates across the IGTO device, such as forming squares or hexagons, or, alternatively, the gates may be formed in parallel lines and interconnected at both ends by perpendicular trenches acting as busses. The gate material in the bus trenches is electrically conductive and is connected to the metal gate electrode 44, such as along the perimeter of the die. The various other components in the IGTO device 32 are connected in parallel so each repeated “cell” conducts a small portion of the total current.
The device 32 includes an n-epi layer 50, a p-well 36, insulated gate material 38, an oxide layer 39 within the trenches, an n+ layer 40 between the vertical gates, a cathode electrode 42, an anode electrode 54 contacting the p+ substrate 52, a gate electrode 44, and dielectric regions 46 patterned to insulate the metal from certain areas. The gate material 38 for all cells (forming interconnected vertical gate regions) is electrically connected to the metal gate electrode 44 via the gate material 56. The p-well 36 surrounds the gate structure, and the n− epi layer 50 extends to the surface around the p-well 36.
Such IGTO devices have a relatively high current density when on. In contrast, insulated gate bipolar transistors (IGBTs) generally have a lower current density when on. Accordingly, for at least high current applications, such IGTO devices are preferred.
The basic operation of the IGTO device is as follows.
An NPNP semiconductor layered structure is formed. In FIG. 1, there is a PNP transistor formed by the p+ substrate 52, the n− epi layer 50, and the p-well 36. There is also an NPN transistor formed by the n-epi layer 50, the p-well 36, and the top n+ layer 40. The top of the p-well 36 is shorted to the n+ layer 40 by the cathode electrode 42, outside of the cross-section, by periodically opening up portions of the n+ layer 40 to allow the cathode electrode 42 to directly contact the surface of the exposed p-well 36.
When a “forward bias” voltage polarity is applied between the bottom anode electrode 54 and the cathode electrode 42, but without a sufficiently positive gate bias, there is no current flow, since the product of the betas (gains) of the vertical PNP and NPN transistors is less than one.
When there is a sufficient positive voltage applied to the gate, and there is a sufficient anode-cathode voltage, electrons from the n+ layer 40 become the majority carriers along the sidewalls and below the bottom of the trenches in an inversion layer, causing the effective width of the NPN base (the portion of the p-well 36 below the trenches) to be reduced. As a result, the beta of the NPN transistor increases to cause the product of the betas to exceed one. This behavior results in “breakover,” when holes are injected into the lightly doped n− epi layer 50 and electrons are injected into the p-well 36 to fully turn on the IGTO device. This condition is the controlled latch-up of the device. Accordingly, the gate bias initiates the turn-on, and the full turn-on is accomplished by the current flow through the NPN and PNP transistors.
When the gate bias is removed, the IGTO device turns off due to the product of the betas being less than one.
The IGTO device of FIG. 1 can only conduct in one direction. If the anode and cathode voltages are reversed, inner diodes of the device are reverse biased. If the potential difference is high, this places a great strain on the device, possibly resulting in damaging breakdown. It is difficult to form a robust device that can withstand such a high reverse voltage.
In some situations, it is desirable to use a bidirectional switch that can rapidly switch currents flowing in opposite directions. This may be done by connecting the IGTO device of FIG. 1 in parallel with an “upside down” IGTO device, and then controlling the two gates accordingly, depending on the polarity of the anode-cathode voltage. However, as mentioned above, the reverse biasing of one of the IGTO devices greatly stresses that device. Further, connecting two separate IGTO devices in parallel (including a series diode for each) adds real estate and cost to the circuit.
What is needed is a design for a robust bidirectional IGTO device that does not have the drawbacks of the devices mentioned above.